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Operation
Now the ESSI can be serviced by polling, interrupts, or DMA. Once the ESSI is enabled (Step 3),
operation starts as follows:
1.
2.
3.
For internally generated clock and frame sync, these signals start activity immediately
after the ESSI is enabled.
The ESSI receives data after a frame sync signal (either internally or externally
generated) only when the receive enable (RE) bit is set.
Data is transmitted after a frame sync signal (either internally or externally generated)
only when the transmitter enable (TE[2–0]) bit is set.
7.3.3 Exceptions
The ESSI can generate six different exceptions. They are discussed in the following paragraphs
(ordered from the highest to the lowest exception priority):
ESSI receive data with exception status:
Occurs when the receive exception interrupt is enabled, the receive data register is full,
and a receiver overrun error has occurred. This exception sets the ROE bit. The ROE bit is
cleared when you first read the SSISR and then read the Receive Data Register (RX).
ESSI receive data:
Occurs when the receive interrupt is enabled, the receive data register is full, and no
receive error conditions exist. A read of RX clears the pending interrupt. This error-free
interrupt can use a fast interrupt service routine for minimum overhead.
ESSI receive last slot interrupt:
Occurs when the ESSI is in Network mode and the last slot of the frame has ended. This
interrupt is generated regardless of the receive mask register setting. The receive last slot
interrupt can signal that the receive mask slot register can be reset, the DMA channels can
be reconfigured, and data memory pointers can be reassigned. Using the receive last slot
interrupt guarantees that the previous frame is serviced with the previous setting and the
new frame is serviced with the new setting without synchronization problems.
Note:
The maximum time it takes to service a receive last slot interrupt should not exceed N
– 1 ESSI bits service time (where N is the number of bits the ESSI can transmit per
time slot).
ESSI transmit data with exception status:
Occurs when the transmit exception interrupt is enabled, at least one transmit data register
of the enabled transmitters is empty, and a transmitter underrun error has occurred. This
exception sets the SSISR[TUE] bit. The TUE bit is cleared when you first read the SSISR
and then write to all the transmit data registers of the enabled transmitters, or when you
write to TSR to clear the pending interrupt.
ESSI transmit last slot interrupt:
Occurs when the ESSI is in Network mode at the start of the last slot of the frame. This
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
7-7
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